This patent application claims priority based on Japanese patent application, H11-99276 filed on Apr. 6, 1999 and H11-290042 filed on Oct. 12, 1999, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a test device and a method of testing an electronic device having a plurality of input pins, and more particularly to a test device and a method of testing an electronic device having an input pin to which analog signals are to be input.
2. Description of the Related Art
Conventionally, a test device for testing an electronic device such as an integrated circuit having analog circuits and digital circuits therein is known.
FIG. 1 shows a structure of a conventional test device. The test device comprises digital circuits and analog circuits. The test device is capable of testing an electronic device having a plurality of digital pins for inputting and outputting digital signals and a plurality of analog pins for inputting and outputting analog signals. The electronic device to be tested by the test device will be referred to as a DUT (a device under test) hereinafter.
The DUT 100 shown in FIG. 1 includes analog circuits such as a programmable gain amplitude (PGA), a low pass filter (LPF), an analog to digital converter (ADC) and a digital to analog converter (DAC). The DUT 100 shown in FIG. 1 also includes digital circuits such as logic circuits including a memory interface and a central processing unit (CPU), a plurality of analog pins APIN and a plurality of digital pins DPIN. The analog pins APIN are used for inputting and outputting analog signals to and from the analog circuits of the DUT 100. The digital pins DPIN are used for inputting and outputting digital signals to and from the digital circuits of the DUT 100.
The test device includes a clock generator 101, a pattern generator 103, a digital pin electronic assembly 105, a digital analog synchronous circuit 107, an arbitrary waveform generator (AWG) 109, an analog pin electronic assembly 111, and a digitizer 113. The clock generator 101 generates a predetermined clock signal. The pattern generator 103 generates a plurality of test patterns using digital signals based on the clock signal generated by the clock generator 101. The digital signals of the test patterns are supplied to the plurality of digital pins DPIN of the DUT 100.
The digital pin electronic assembly 105 supplies the digital signals of the test patterns generated by the pattern generator to predetermined input digital pins DPIN of the DUT 100. The digital pin electronic assembly 105 receives output signals from the predetermined output digital pins DPIN of the DUT 100. The digital analog synchronous circuit 107 synchronizes the pattern generator 103 and the AWG 109. The AWG 109 generates and outputs one kind of predetermined analog signal.
The analog pin electronic assembly 111 includes signal lines and a plurality of switches SW. The analog signal generated by the AWG 109 is input to a predetermined input analog pin APIN of the DUT 100 by commuting the switches SW. The analog signal output from a predetermined output analog pin APIN of the DUT 100 is input to the digitizer 113 by commuting the switches SW. The digitizer 113 measures and analyzes frequency characteristics and group delays based on the analog signal output from the DUT 100.
FIG. 2 shows a structure of the arbitrary waveform generator of the conventional test device. The arbitrary waveform generator 109 includes a central processing unit (CPU) 109A, a waveform memory 109B, a sequence control unit 109C, a full-scale digital analog converter (full-scale DAC) 109D, an off-set digital analog converter (off-set DAC) 109E, a digital analog converter (DAC) 109F, a low pass filter (LPF) 109G, an amplitude 109H, an attenuator (ATT) 109I, and a correction calculator 109J.
Operations executed by the arbitrary waveform generator 109 under the control of the CPU 109A will be described in the following. The sequence controller 109C sequentially reads out data from the waveform memory 109B based on the clock signal output from the clock generator 101 and the control of the digital analog synchronous circuit 107, to output to the DAC 109F. The DAC 109F converts data input from the waveform memory 109B to a predetermined data format to output to the LPF 109G, based on gain signals output from the full-scale DAC 109D and the clock signal output from the clock generator 101.
The LPF 109G filters the data input from the DAC 109F for output to the amplitude 109H. The amplitude 109H adds off-set values output from the off-set DAC 109E to the analog signal output from the LPF 109G to output to the ATT 109I. The ATT 109I adjusts to attenuate the voltage of the analog signal to within a predetermined range for output to the analog pin electronic assembly 111. The correction calculator 109J calculates the analog signal output from the ATT 109I. The result of the calculation by the correction calculator 109J is used for correcting the signal.
FIG. 3 shows a process of generating the analog signal using the conventional test device. Firstly, an analog signal having a desired waveform is selected for supply to the DUT 100 (S100) A sampling frequency fs for sampling the analog signal (S102) is determined. Generally, the sampling frequency fs is determined by dividing the period of the waveform of the analog signal by the memory lengths which the waveform memory 109B can store. The selected analog signal is generated, sampled in accordance with the determined sampling frequency fs, and stored in the waveform memory 109B (S104). The data stored in the waveform memory 109B is sequentially read out when the analog signal is to be generated. Then, the analog signal is output (S106).
It is necessary to supply a plurality of analog signals to the electronic device simultaneously, or to supply synchronized digital signals and analog signals to the electronic device, in order to test an electronic device having analog circuits and digital circuits therein as described above.
However, in the above described conventional test device, the test device needs to include a plurality, of arbitrary waveform generators to supply a plurality of analog signals to the electronic device at same time. This leads to a test device that is large and expensive. The test device needs to include the digital analog synchronous circuit to synchronize the analog signals and the digital signals. The digital analog synchronous circuit has a complicated structure that makes the test device expensive. There is another problem where even with this digital analog synchronous circuit, the digital signals and the analog signals cannot be precisely synchronized for supply to the electronic device. It is necessary for the test device to be able to easily adjust the timing of generation of the analog signals and the digital signals to be supplied to the electronic device.
Therefore, it is an object of the present invention to provide a testing technique that overcomes the above issues in the related art. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
The test device according to the present invention is for electrically testing an electronic device having a plurality of input pins. An aspect of the present invention comprises a pattern generator generating a plurality of test patterns using digital signals based on data defining a plurality of test patterns including an analog signal test pattern and a digital signal test pattern to be supplied to said electronic device, said test patterns being input to said plurality of input pins of said electronic device and a first filter converting said digital signals of said analog signal test pattern to analog signals. Said plurality of test patterns including said analog signal test pattern are supplied to said electronic device.
The first filter converts said digital signals to said analog signals. Said digital signals are digital signals of said analog signal test pattern and a low pass filter or a band pass filter, as said first filter, converts said digital signals to said analog signals.
In this structure, the test pattern of the analog signal test pattern is generated as digital signals. Therefore, the test for analog signals and the test for digital signals can be synchronized when necessary. As the pattern generator generates the test pattern of the analog signals, there is no need to include, for example, an arbitrary waveform generator. For example, delta-sigma modulation is used for generating the analog signal test pattern as the digital signals.
The test device may further comprise a display unit displaying a chart in which both of said analog signal test pattern and said digital signal test pattern are shown in accordance with a time base. The test device may further comprise a time setting unit setting time for supply of said analog signal test pattern and said digital signal test pattern to said electronic device. The test device may comprise a second filter having a specific difference from said first filter and converting said digital signals of said test pattern generated by said test pattern generator to analog signals; and a filter switching unit selecting either of said analog signals of said test patterns converted by said first filter and said second filter to supply to said electronic device.
An aspect of method for electrically testing an electronic device having a plurality of input pins according to the present invention comprises generating a plurality of test patterns using digital signals, based on data defining said plurality of test patterns including an analog signal test pattern and a digital signal test pattern to be supplied to said electronic device, to be input to said plurality of input pins of said electronic device; converting said digital signals of said analog signal test pattern to analog signals; and supplying said plurality of test patterns including said analog signal test pattern to said electronic device.
Another aspect of method for electrically testing an electronic device having a plurality of input pins according to the present invention comprises first to third steps. The first step generates digital data based on a single timing signal, said digital data including first digital data for analog signals for testing said analog circuit and second digital data for digital signals for testing said digital circuit. The second step converts said first digital data for analog signals for testing said analog circuit to analog signals. The third step supplies said second digital data for digital signals for testing said digital circuit to said digital circuit of said electronic device and said analog signals to said analog circuit of said electronic device.
Said first step may generate said first digital data for analog signals for testing said analog circuit as a part of said digital data using delta-sigma modulation. Said second step may convert said first digital data to said analog signals using band pass filtration or low pass filtration.
This summary of the invention does not necessarily describe all essential features. The invention may also be a sub-combination of these described features.